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topology.h
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1 /* Copyright (c) 2011 Wildfire Games
2  *
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22 
23 /*
24  * detection of CPU and cache topology.
25  * thread-safe, no explicit initialization is required.
26  */
27 
28 #ifndef INCLUDED_X86_X64_TOPOLOGY
29 #define INCLUDED_X86_X64_TOPOLOGY
30 
31 #include "lib/sysdep/arch/x86_x64/apic.h" // ApicId
32 
33 namespace topology {
34 
35 //-----------------------------------------------------------------------------
36 // cpu
37 
38 // the CPU topology, i.e. how many packages, cores and logical processors are
39 // actually present and enabled, is useful for parameterizing parallel
40 // algorithms, especially on NUMA systems.
41 //
42 // note: OS abstractions usually only mention "processors", which could be
43 // any mix of the above.
44 
45 /**
46  * @return number of *enabled* CPU packages / sockets.
47  **/
48 LIB_API size_t NumPackages();
49 
50 /**
51  * @return number of *enabled* CPU cores per package.
52  * (2 on dual-core systems)
53  **/
54 LIB_API size_t CoresPerPackage();
55 
56 /**
57  * @return number of *enabled* logical processors (aka Hyperthreads)
58  * per core. (2 on P4 EE)
59  **/
60 LIB_API size_t LogicalPerCore();
61 
62 /**
63  * @return index of processor package/socket in [0, NumPackages())
64  **/
65 LIB_API size_t PackageFromApicId(ApicId apicId);
66 
67 /**
68  * @return index of processor core in [0, CoresPerPackage())
69  **/
70 LIB_API size_t CoreFromApicId(ApicId apicId);
71 
72 /**
73  * @return index of logical processor in [0, LogicalPerCore())
74  **/
75 LIB_API size_t LogicalFromApicId(ApicId apicId);
76 
77 /**
78  * @param idxPackage, idxCore, idxLogical return values of *FromApicId
79  * @return APIC ID (see note at AreApicIdsReliable)
80  **/
81 LIB_API ApicId ApicIdFromIndices(size_t idxPackage, size_t idxCore, size_t idxLogical);
82 
83 
84 //-----------------------------------------------------------------------------
85 // L2 cache
86 
87 // knowledge of the cache topology, i.e. which processors share which caches,
88 // can be used to reduce contention and increase effective capacity by
89 // assigning the partner processors to work on the same dataset.
90 //
91 // example: Intel Core2 micro-architectures feature L2 caches shared by
92 // two cores.
93 
94 /**
95  * @return number of distinct L2 caches.
96  **/
97 LIB_API size_t NumCaches();
98 
99 /**
100  * @return L2 cache number (zero-based) to which the given processor belongs.
101  **/
102 LIB_API size_t CacheFromProcessor(size_t processor);
103 
104 /**
105  * @return bit-mask of all processors sharing the given cache.
106  **/
107 LIB_API uintptr_t ProcessorMaskFromCache(size_t cache);
108 
109 } // namespace topology
110 
111 #endif // #ifndef INCLUDED_X86_X64_TOPOLOGY
size_t CoreFromApicId(ApicId apicId)
Definition: topology.cpp:268
size_t NumPackages()
Definition: topology.cpp:244
Definition: topology.cpp:41
size_t LogicalPerCore()
Definition: topology.cpp:256
size_t PackageFromApicId(ApicId apicId)
Definition: topology.cpp:274
size_t LogicalFromApicId(ApicId apicId)
Definition: topology.cpp:262
size_t CoresPerPackage()
Definition: topology.cpp:250
size_t NumCaches()
Definition: topology.cpp:454
ApicId ApicIdFromIndices(size_t idxLogical, size_t idxCore, size_t idxPackage)
Definition: topology.cpp:281
u8 ApicId
Definition: apic.h:26
uintptr_t ProcessorMaskFromCache(size_t cache)
Definition: topology.cpp:467
size_t CacheFromProcessor(size_t processor)
Definition: topology.cpp:460