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cache.cpp File Reference
#include "precompiled.h"
#include "lib/sysdep/arch/x86_x64/cache.h"
#include "lib/bits.h"
#include "lib/alignment.h"
#include "lib/module_init.h"
#include "lib/sysdep/os_cpu.h"
#include "lib/sysdep/arch/x86_x64/x86_x64.h"
Include dependency graph for cache.cpp:

Classes

struct  x86_x64::CPUID2::Characteristics
 

Namespaces

 x86_x64
 
 x86_x64::AMD
 
 x86_x64::CPUID4
 
 x86_x64::CPUID2
 

Macros

#define CACHE(descriptor, flags, totalSize, assoc, entrySize)   { descriptor, assoc, -entrySize, flags | ((totalSize)/(entrySize)) }
 
#define TLB(descriptor, flags, entrySize, assoc, numEntries)   { descriptor, assoc, numEntries, flags | (entrySize) }
 

Typedefs

typedef u8 x86_x64::CPUID2::Descriptor
 
typedef std::vector< Descriptor > x86_x64::CPUID2::Descriptors
 

Enumerations

enum  x86_x64::CPUID2::Flags {
  x86_x64::CPUID2::L1 = 1, x86_x64::CPUID2::L2, x86_x64::CPUID2::L3, x86_x64::CPUID2::I = 0x04,
  x86_x64::CPUID2::D = 0x08, x86_x64::CPUID2::U = I|D
}
 
enum  x86_x64::CPUID2::DescriptorFlags { x86_x64::CPUID2::SKIP_CACHE_DESCRIPTORS = 1, x86_x64::CPUID2::NO_LAST_LEVEL_CACHE = 2, x86_x64::CPUID2::PREFETCH64 = 64, x86_x64::CPUID2::PREFETCH128 = 128 }
 

Functions

static void x86_x64::AddCache (const x86_x64::Cache &cache)
 
static void x86_x64::AddTLB (const x86_x64::Cache &tlb)
 
static x86_x64::Cache x86_x64::AMD::L1Cache (u32 reg, x86_x64::Cache::Type type)
 
static x86_x64::Cache x86_x64::AMD::L2Cache (u32 reg, x86_x64::Cache::Type type)
 
static x86_x64::Cache x86_x64::AMD::L3Cache (u32 reg, x86_x64::Cache::Type type)
 
static x86_x64::Cache x86_x64::AMD::TLB1 (u32 reg, size_t bitOffset, size_t pageSize, x86_x64::Cache::Type type)
 
static x86_x64::Cache x86_x64::AMD::TLB2 (u32 reg, size_t bitOffset, size_t pageSize, x86_x64::Cache::Type type)
 
static void x86_x64::AMD::AddTLB2Pair (u32 reg, size_t pageSize)
 
static void x86_x64::AMD::DetectCacheAndTLB ()
 
static bool x86_x64::CPUID4::DetectCache ()
 
static void x86_x64::CPUID2::AppendDescriptors (u32 reg, Descriptors &descriptors)
 
static Descriptors x86_x64::CPUID2::GetDescriptors ()
 
static const Characteristics * x86_x64::CPUID2::CharacteristicsFromDescriptor (Descriptor descriptor)
 
static bool x86_x64::CPUID2::HandleSpecialDescriptor (Descriptor descriptor, size_t &descriptorFlags)
 
static void x86_x64::CPUID2::DetectCacheAndTLB (size_t &descriptorFlags)
 
static Status x86_x64::DetectCacheAndTLB ()
 
const x86_x64::Cachex86_x64::Caches (size_t idxCache)
 

Variables

static const size_t x86_x64::maxTLBs = 2*2*4
 
static size_t x86_x64::numTLBs = 0
 
static const size_t x86_x64::numCaches = x86_x64::Cache::maxLevels * 2 + maxTLBs
 
static Cache x86_x64::caches [numCaches]
 
static const size_t x86_x64::AMD::associativityTable [16]
 
static const u8 x86_x64::CPUID2::F = x86_x64::Cache::fullyAssociative
 
static const Characteristics x86_x64::CPUID2::characteristicsTable []
 

Macro Definition Documentation

#define CACHE (   descriptor,
  flags,
  totalSize,
  assoc,
  entrySize 
)    { descriptor, assoc, -entrySize, flags | ((totalSize)/(entrySize)) }
#define TLB (   descriptor,
  flags,
  entrySize,
  assoc,
  numEntries 
)    { descriptor, assoc, numEntries, flags | (entrySize) }